A time-to-digital-converter is often used to measure timing in a gamma ray detector. A TDC accurately converts the realization of an event into a number than can be related to the time the event occurred. Various methods exist to perform this task. Among others, counting a large number of very fast logic transitions between coarse clock cycles has been used to perform this task. In some cases, it may be desirable to indicate the occurrence of a series of events known to be generated sequentially. For instance, the time a rising signal takes to reach a pre-determined set of threshold values can be very useful information.
Time-to-digital converters have also been implemented with a variety of architectures, such as a classic delay chain having a single chain of identical delay elements connected in series or a Vernier delay chain.
An essential component of time-of-flight positron emission tomography (PET) systems is the time-to-digital converters that are used to measure the arrival time of detected photons at the detector. The measured time can be used to create a bound on the line-of-response, which can be used to estimate the position at which the positron emission event took place. As the accuracy of the TDC increases the bound becomes tighter, providing more accurate position information.
The accuracy of the delay-chain-based TDC is dependent upon the size in time of the sampled steps of the delay chain. In FPGA-based implementations of delay-chain TDCs, the sampled steps can vary by a significant amount depending upon the physical limitations of the FPGA. In some cases variations of up to ten times have been observed.
While coarse offsets can be designed into an FPGA-based implementation and utilized to improve timing accuracy over single-edge delay chain based TDCs, there exists significant manufacturing-based variation in the speed of on-chip circuits. These variations will affect the optimal delay between edges that should be used to extract the maximal accuracy from the collective TDC circuit. Thus, there is a need to compensate for the manufacturing variation so as to increase the timing accuracy of the implemented TDC on every chip.